The electronics industry continues to rely upon advances in semiconductor technology to realize higher-functioning devices in more compact areas. For many applications, realizing higher-functioning devices requires integrating a large number of electronic devices into a single silicon wafer. As the number of electronic devices per given area of the silicon wafer increases, the manufacturing process becomes more difficult.
A wide variety of techniques have been used in IC devices to ensure that, once they are manufactured, they operate fully in compliance with their intended design and implementation specifications. Many of the more complex IC designs include circuits that permit in-circuit testing via the IC access pins. The IEEE 1149.1 JTAG recommendation, for example, provides a test circuit architecture for use inside such ICs. This architecture includes a test access port (TAP) controller coupled to the IC pins for providing access to and for controlling various standard features designed into such ICs. Some of these features are internal scan, boundary scan, built-in test and emulation.
The JTAG recommendation was developed with the understanding that such IC designs would be using only one test access port controller. Sometime after its initial development, however, many IC's are being designed with multiple "core" circuits, such as multiple CPUs, with each core circuit including its own TAP controller. Typically, separate IC pins are used to select one of the TAP controllers for testing and/or debugging the IC. This is problematic, however, in IC applications that require an increasing number of core circuits without increasing the circuit area of the IC and/or the number of IC pins.
One approach that attempts to overcome such difficulty involves use of an internally implemented circuit for selecting which of the TAP controllers is activated during a test/debug mode of operation inside the TAP controller itself. This approach requires a change to the existing structure of the TAP controllers so that special signals can be drawn from and fed to each TAP controller, and requires that each TAP controller have knowledge that it is enabled at a given time. For many applications, however, changing the design of the established TAP controller is expensive. Further, for certain applications, requiring that each TAP controller have knowledge that it is enabled at a given time adversely removes a desired degree of transparency.
For further information concerning with the above issues, reference may be made to an article entitled, "An IEEE 1149.1 Based Test Access Architecture for ICs with Embedded Cores," by Lee Whetsel, and to IEEE Std. 1149.1-1990, and 1149.1-1993, each of which is incorporated herein by reference.
Another IEEE JTAG related problem, also directed to ICs having multiple core circuits, concerns "Scan Chain Control" signaling, which is a JTAG-specified feature. As discussed in connection with the above-referenced applications, Scan Chain Control can be implemented using a Test Link Module (TLM) to pass a test instruction (e.g., TLM Select instruction) to the TAP controller as part of the enablement of a TAP controller. However, certain types of multiple "core" circuits need to maintain the currently-stored instruction for execution rather than the TLM-passed test instruction. In such applications, using Scan Chain Control to transfer control is impractical because passing the test instruction displaces the current instruction and thereby removes the TAP controller's ability to execute the current instruction. This typically results in a failed control transfer. This problem is especially apparent when debugging such multi-core ICs, in that a core in a debug mode is dependent upon the currently-stored instruction and transferring control to another TAP controller requires exiting from the debug mode for the current core.
One approach for addressing the above-characterized Scan Chain Control problem is to duplicate the instructions for each of the TAP controllers. This, however, requires changes to the existing core's instruction register and decoder and, therefore, is not a practical solution for many applications. For further information regarding this type of approach, reference may be made to the above-mentioned article by Lee Whetsel.
For some types of multiple core circuits, the core circuit only has boundary scan chain for the exclusive use of its pins but not for the purpose of selecting the TLM. Because this type of core circuit cannot pass boundary scan chain for the TLM, the TLM control provided via the Scan Chain Support function fails. Similarly, for the core circuit that has no external scan-chain support, there is no way to control transfer back and forth between the core and the TLM.